This invention relates to an input protection device for static electricity discharges at the input stages of semiconductor integrated circuits, and particularly to such protection devices for improving the signal delay time at the input stage of the integrated circuits.
In IC design, protection devices against discharge of static electricity charges are provided at the input stage of the ICs. Most semiconductor ICs, such as semiconductor memories have such protection devices in order to protect them from destruction resulting from instantaneous static charges coming from the human body or other sources.
A conventional protection device against static charge at an input stage will now be described with reference to FIG. 1 which shows one example of such conventional device.
FIG. 1(A) is a plan view of a layout of the input stage of a conventional integrated circuit and shows the charge collection area 2 connected with Vss and the input path area 3 connected with the input pad.
FIG. 1(B) is a cross-sectional view along the line a--a' of FIG. 1(A) and shows an n+ diffusion layer of the input path area 3 and an n+ diffusion layer of the charge collection area 2 on a p type Si-substrate.
FIG. 1(C) is an equivalent circuit diagram of the device of FIGS. 1A and 1B.
FIG. 1(C) shows an input pad 4 which is connected to the input path area 3. The input signal is applied to the pad 4 and is conveyed to the first or input stage of the integrated circuit (not shown) via the area 3. There is some delay of the signal coming through the input pad 4 by the diffusion layer resistance R3 of the input path area 3. Static charges which come through the input pad 4 are collected in the charge area 2 via the transistor 1. As a result, the IC is protected from destruction by the static charges. But, the path of the input circuit 3 should be long in order to increase the effective charge collection area, which causes an increase of the diffusion resistance. Thus, the input area 3 provides a long delay time. This, in turn, causes a decrease in the performance of the overall integrated circuit.